Various techniques known in the art can be used to fabricate a semiconductor device such as a transistor. In general, these techniques involve repeating, with variations, a number of characteristic steps or processes. One of these characteristic steps or processes involves applying a layer of material to an underlying substrate or to a preceding layer, and then selectively removing the material using, for example, an etch process. Another of the characteristic steps or processes involves adding dopant materials (e.g., an ion implant) to the substrate or to one or more of the subsequent layers. Using these characteristic processes, a transistor, generally comprising different types of material, can be accurately formed.
One characteristic of a transistor is its “threshold voltage,” generally defined as the input voltage at which the output logic level of the transistor changes state. Another definition of the term “threshold voltage” is the gate voltage above which the transistor becomes conductive. The operational speed of a transistor is a function of its threshold voltage. To increase speed, the threshold voltage is decreased. However, there is a tradeoff; with decreased threshold voltage, the drive current and leakage current of the transistors are increased, increasing power consumption. Thus, depending for instance on the planned application of the transistor, a manufacturer will select a particular threshold voltage for the transistor, based on factors including speed and power consumption.
Types of transistors known in the art include those commonly referred to as NMOS (negative-channel metal-oxide semiconductor) devices and PMOS (positive-channel metal-oxide semiconductor) devices. The threshold voltage of these types of devices is dependent on the original doping concentration of the silicon substrate used as the foundation for forming the transistor. For PMOS devices, the threshold voltage can be reduced by adjusting the original doping concentration using another, subsequent implantation of dopant into the substrate. This latter implantation may be generally referred to as the “threshold adjust.” Typically, the threshold adjust uses boron ions (or ions that include boron, such as BF2 ions) as the dopant, in which case the threshold adjust may be referred to as the “boron adjust.” By adding dopant, particularly a p-type dopant that includes boron, the threshold voltage of a PMOS device is lowered.
As mentioned above, NMOS devices having a particular threshold voltage can be fashioned by specifying the appropriate original doping concentration. However, according to the conventional art, a threshold adjust process for reducing the threshold voltage of NMOS devices is lacking.
One conventional approach that provides higher-threshold voltage and lower-threshold voltage NMOS devices involves using a first set of masks to create one type of devices (e.g., higher-threshold voltage devices) and a second set of masks to create the other type of devices (e.g., lower-threshold voltage devices). Using this approach, the substrate is masked and the exposed areas of the substrate are implanted with dopant at a concentration that establishes, for instance, a higher-threshold voltage for the NMOS devices. A different mask is subsequently used to cover the implanted regions and expose new regions of the substrate to implantation. These regions of the substrate are implanted with dopant at a concentration that establishes a lower-threshold voltage for the NMOS devices. These steps can be repeated to form higher-threshold voltage and lower-threshold voltage PMOS devices.
A disadvantage to this approach is its inefficiency. According to the approach just described, four masking steps and four implant steps are used to form higher-threshold voltage and lower-threshold voltage NMOS and PMOS devices.
Therefore, a method for fabricating NMOS devices, as well as PMOS devices, that is more efficient than the conventional art would be an improvement. The present invention provides such an improvement.